Synopsys and LSI Logic to Jointly Develop Models for Hardware/Software Co-Verification
SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 29, 1999--Synopsys, Inc. (Nasdaq:SNPS) and LSI Logic Corp. (Nasdaq:LSI) have agreed to jointly develop high-performance, cycle-accurate models of popular LSI Logic microprocessor cores for hardware/software co-verification.
The first model to be released under the new agreement is the TinyRISC EZ4102 MIPS compliant processor core. It is available immediately from Synopsys. Models developed under this agreement will be verified against the LSI Logic test suite to ensure their accuracy.
Hardware/software co-verification with Synopsys' Eaglei(R) environment allows designers to significantly improve product quality and reduce design time by allowing application and OS software to be run on hardware long before physical prototypes are available. This capability is essential for successful verification of complex system-on-chip designs. Design teams who have adopted this methodology have typically reported design cycle reductions of at least 20%.
The LSI Logic EZ4102 MIPS Processor architecture focuses on the cost-sensitive consumer electronics embedded market. With MIPS16 support for code compression, the EZ4102 is well suited for applications such as set-top boxes, digital TV, DVD, digital cameras, GSM digital cellular phones, small office/home office (SOHO) network routers, convergence PCs, and a wide array of emerging embedded applications including smart cards for banking, toll booths, and shopping; security ID, wireless communications, cable modems, and integrated automotive entertainment and control units.
All of these end products have a significant software component, which must run in concert with the custom hardware, making early verification of the integration of the hardware and software design elements essential to achieve aggressive time-to-market goals.
"LSI Logic has seen growing customer demand for a comprehensive verification tool suite, in addition to IP building blocks," said Karen O'Connell, director of LSI Logic's Consumer Products Division, "By combining Synopsys' model development technology and engineering expertise with LSI Logic's in-depth processor knowledge, we are able to efficiently meet the growing demand from our customers for access to the co-verification models they need for successful early integration of hardware and software."
The open Synopsys Eaglei architecture ensures that the new LSI Logic EZ4102 model will be useful to designers using the widest available range of software development tools, real time operating systems and hardware design tools, including cycle-based simulators and emulators.
The EZ4102 Eaglei model implements both 32-bit instructions and 16-bit instructions for code compression. It supports both big and little endian modes. The cache of the model is fully configurable both at simulation startup time and on the fly, to allow the user to simulate various EZ4102 cache configurations.
Interrupt handling, MMU, internal write buffers, BIU and Cache Controller (BBCC) are also modeled. This allows software designers to accurately measure code performance and hardware designers to have a very fast, accurate model of the activity of the processor buses and pins.
For more information on Synopsys model support for LSI Logic, contact your local Synopsys representative, email verify@synopsys.com or, in North America, call 800/346-6335.
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