Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: THE WATSONYOUTH who wrote (73406)	9/29/1999 11:43:00 AM
From: Elmer	Read Replies (1) of 1573433

Re: "In my experience, the typical guard band on these processors is 5% to 10%. " It would seem far simplier to me to guardband the VCC rather than the frequency, and it would accomplish the same thing. In an attempt to keep test time at a minimum, the question would be, which requires the least time? A voltage switch or a reload of the timing registers? With the constant concern of violating tester timing restrictions, having multiple timing templates could be a major resource consuming task. Furthermore, going to 800Meg or 1Gig core speed would require ultra high speeds on the cache bus even at only 1/2 core speeds. Extremely difficult to test in a production environment. All this points out the enormous value of low defect density, allowing large on-die caches. No need to test the BSB because there isn't any. Much lower tester speeds and much lower pin count thus much lower capitol costs. EP

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next