Rob, <So if L2 does > 10 Gig what good does that do when it can only be fed at 4.2?>
I don't know if we're talking on the same wavelength here. L2 bandwidth is back-side bus, independent of front-side bus. For example, let's look at Pentium III Xeon 500 MHz on a 100 MHz bus. Its BSB has a bandwidth of 4.8 GB/sec, but its FSB has a bandwidth of 0.8 GB/sec. Merced will have more than 10 GB/sec of BSB bandwidth. FSB bandwidth hasn't been revealed yet, but it's obviously going to be much smaller.
<Why can't Intel pin down accurate performance numbers given very good simulators?>
They can. They just aren't in the habit of revealing performance estimates by the numbers, at least not this early. A lot of those numbers are still up in the air because of confidential variables like starting clock speeds, correlation between performance in real hardware vs. simulators, release date, etc.
<I see them too at www.news.com (Intel is a sponsor)>
I thought Intel sold its share of CNET, which is why you don't see the disclaimer "Intel is an investor in CNET" anymore. It's not like CNET forgot, either, since they were pretty religious about the disclosure.
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