Hi KZNerd; I'm not feeling very well tonight, so I've been reading in bed a lot. But I had some more hazy thoughts...
There was some talk about solving the signal integrity problem by requiring ECC, in addition to two RIMM slots. If this did become operative, and memories have had to use this technique in the past, it would add another 12% or so to the die penalty for RDRAM versus other technologies.
The thing that is really bothering me is how little real information there is out there about the technical problems and when they are likely to be solved. But I did some thinking about that Micron Electronics advertisement pulling the chains of the Rambus coalition.
Micron Semi makes RDRAMs, Micron Electronics has to have put together prototypes of RDRAM based machines, at least, so you would guess that they would know quite a bit about what kind of trouble Intel and Rambus were in. We all know that they hate Rambus with a purply passion, and probably aren't too hot on Intel, either.
So I got to wondering about that ad campaign. Would they have released it if they suspected that Intel was going to start shipping a decent version of Camino while their ads were still running? I don't think so.
I think that ads have to be purchased at least a couple of weeks into the future. So my suspicion is that Micron Semi / Micron Electronics knows something about the problem which isn't pretty: that there is no easy solution, maybe even that Camino is being turned.
In addition, a Camino turn is consistent with the "recall" of all the Camino chips, not just systems with two RIMM sockets.
I have no other way of knowing, but when your customers start taking out ads making fun of you, you have to start wondering. Maybe they are looking to go with more AMD parts (hope, hope, hope), and know that AMD is going to license some of their processor designs for cash and second source availability.
By the way, I've been getting the urge to write a Java applet that will allow you to simulate signals passed down a 3-RIMM Rambus channel, assuming that the MB traces and RIMM traces and termination have various impedances, which differ. The reason for this, is that Intel specifies (in a pdf file,) what kinds of tolerances the MBs have to be built to. I seem to recall that the MB impedance was 10%. Sure would be a cool simulation, but it sounds a little too much like work.
-- Carl |
