Hi Cirruslvr; Re all this talk about yields...
From an economic point of view, I think the best way to measure yield is by the ratio of used silicon area to total wafer silicon area. Sure you get fewer chips if they are bigger, but they have more stuff on them - what really matters is how much silicon you put in the recycle bin. The increase in integration generally provides benefits in terms of reduced total package costs, increased speed, decreased total power consumption, increased reliability, etc.
Those advantages of increased integration are what have driven this industry to putting many millions of transistors on a chip. So I think the above ratio is the one to use. It is almost equal to the ratio of good die over total die, the difference being silicon area wasted at the wafer edge, or used for process control.
If you use this metric for evaluating yield, you more or less (see note below) always conclude that the yield decreases when you increase the size of the die. But if the defect density is low enough (or the circuits have enough redundant logic), the penalty for combining two circuits into one chip can be very, very small, much smaller than the increased packaging costs of separating the two logic blocks. It's a complicated matter of engineering trade off, just like almost every other non-trivial engineering decision.
Every foundry I've dealt with has been extremely reticent about sharing their defect density. Who knows what AMD is doing, maybe they told Anand, but I doubt it. If AMD isn't getting great yields, they sure aren't pricing their product as if that were the case.
-- Carl
P.S. Note that it is easy to show that there can be reasonable examples of die size, wafer size, and defect density, where an increase in the die size (all other things being "equal",) results in an increase in yield, as defined above. Being a mathematician, and loving a good problem, I'll let those of you who haven't written down the equations figure out how this could happen. |
