Intel Investors - Intel's ITanium (Merced) can execute 6 Simultaneous Instructions - in optimized Compiler Code.
"The processor will perform six instructions per clock cycle, have what is called a 10-stage pipeline for executing instructions, and be capable of 6 billion floating point operations per second. "
Of course, Nathan BlowHard Brookwood quickly found a way to trivialize this capability !
Paul
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infoworld.com
Intel set to unveil more features of Itanium processor
By Ephraim Schwartz
InfoWorld Electric
Posted at 5:11 PM PT, Oct 4, 1999
On Tuesday, Intel will announce more performance details of the Itanium processor, formerly know as Merced, at the Microprocessor Forum in San Jose.
At the forum, the chip giant will disclose that the Itanium processor will include three levels of on-chip cache, with Level 3 cache offered in a 2MB or a 4MB package. IA-32 processors, like the Pentium II and III, have only two levels of on-chip cache.
Despite the fact that Intel has let out a slow but steady stream of details about the Itanium over the last three years, it seems there are still more details yet to come.
The processor will perform six instructions per clock cycle, have what is called a 10-stage pipeline for executing instructions, and be capable of 6 billion floating point operations per second.
"The Itanium is clearly very powerful. If they could make all of those six billion instructions wholly relevant on a single task that is awesome," said Nathan Brookwood, chief analyst at Insight 64, a microprocessor research organization in Saratoga, Calif.
According to Brookwood, it is more likely that half of those six billion instructions would be used for trial branching
"I would imagine it [Itanium] would do half on a speculative basis. I branched down this path and I don't need to," is how Brookwood described the process.
Previously, 486 processors were capable of only one instruction per cycle, Pentium processors are capable of two instructions per cycle, and Pentium II and Pentium III processors are capable of three instructions per cycle.
"The challenge that Intel has is for their compiler to find six instructions that they can do at every cycle. When it can do that, they will have a big win on their hands," Brookwood said.
"There's a lot of raw horsepower in a Merced [Itanium], as there is a lot of energy in a bolt of lightning or a raging river. Intel's challenge is to harness all of that power to produce a useful result," Brookwood said.
Intel will market the IA-64 processors as the backbone of the "Internet economy," according to Jami Dover, vice president of Intel's Sales and Marketing Group.
Intel officials interviewed declined to reveal the final processor frequency.
Intel Corp., in Santa Clara, Calif., can be reached at www.intel.com.
InfoWorld Editor at Large Ephraim Schwartz is based in San Francisco.
Related story:
Intel brands Merced with new name |
