What we all want - Information
Lots of it in this article -
AMD discloses internally-developed 64-bit architecture
(It's too long to post)
ebns.com
"Adding 64-bit capabilities increases the 104 sq. mm. die size of a 32-bit Athlon processor produced in 0.18-micron technology by only 5 percent, Lapinski said."
So if the SH flops and its X86 is up to Willamette's par, AMD won't have a completely defunct processor with the K8
"More importantly, AMD claims that the combination of a small die size and its 0.18-micron process will allow the company to pack more than one 64-bit X86 microprocessor on a single die. That's important, given the fact that X86 integer instruction performance is closing in on RISC chips, Lapinski said. Through triple-operand, double-precision floating-point instructions that AMD is designing for the new architecture, the company hopes to eliminate the floating-point advantage of RISC chips as well, he said."
I wonder if they are aiming at the 21364's FPU capabilities. I don't remember the number those guys are speculating, but I think it was 3 digit SPECfp95 score. Rob Young can probably comment on that.
"One thing we haven't brought up is the software infrastructure"
That's a biggy of course.
"Next year, the Athlon Ultra for workstations and servers will feature 1 and 2 Mbytes of off-chip, full-speed, 16-way, set-associative Level 2 cache."
"Lapinski also said AMD is evaluating the so-called K6-2 Plus, a 0.18-micron K6-2 reported to include 128 or 256 kbytes of on-chip cache. A third chip without Level 2 cache is also thought to be under consideration, although Lapinski would not divulge details" |
