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Politics : Formerly About Advanced Micro Devices
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To: Elmer who wrote (74150)10/5/1999 11:30:00 PM
From: Cirruslvr  Read Replies (1) of 1572631
 
Elmer - RE: "With a 256 bit databus that's 8x the cache bandwidth of it's predecessor, the PII & PIII, and 4X the bandwidth of Xeon. The cache controller appears to have been "enhanced" to also provide better performance. 4X lower latency on read/store means it gets it sooner as well as faster."

Thanks for the info.

Sounds like this was designed with DRDRAM in mind.

Correct me if I'm wrong.
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