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To: Process Boy who wrote (89563)10/6/1999 12:30:00 PM
From: Saturn V  Read Replies (1) of 186894
 
Thanks for keeping the thread posted on the Coppermine information.

I agree that the Coppermine will improve performance significantly over the PII/Celeron/PIII in memory intensive benchmarks.

Specifically:

A. The Coppermine has a 8-way L2 cache compared to 4-way. This will reduce the incidence of L2 cache miss.

B. The 256 bit wide data path from L2 to L1 will reduce the L1 fill time, slightly reducing the penalty of a L1 cache miss.

C. The deeper bus buffers will reduce the impact of a L2 cache miss. This will allow the system to scale easily as the processor clock speed in increased without a proportional increase in memory speed.

I have worked with memory intensive applications with P2 and I found a 3-7 clock penalty for a L1 miss, and a 30-70 clock penalty for a L2 miss. So I believe that these enhancements will be significant. However if the processor automatically prefetched adjacent pages, explicitly via SSE software or implicitly via hardware, the performance improvements will be even greater. So if the compiler can automatically generate the SSE instructions, even greater performance enhancements are possible.

So it appears the Coppermine architectural tweaks , along with further process optimisations you have alluded to, can keep the Athlon at bay, until Williamette shows up,and shows Intel's seventh generation architecture.

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