Thanks for four outstanding reports and updates on the MPF.
Ref-
<I'm sure other architectural improvements could have been made, maybe perhaps even a bigger L1, but I guess only the L2 was improved because it was easier to do, less risky, and better for time-to-market conditions.>
I think Coppermine designers made an excellent choice. The wide L1-L2 interface and full speed L2, leads to a minimal penalty for a L1 miss . I'll bet that the performance bottleneck is a L2 miss, and the L2-main memory interface. Thus the design resources have gone into minimizing L2 miss incidence, and the penalties for a L2 miss. The more associative L2 cache and deeper buffers for main memory, thus had a major impact. IMHO the impact of a larger L1, would have been minimal.
The Coppermine architecture tweaks appear to have been worthwhile, even though they probably contributed to the schedule slippage.
On the process technology area, Intel has also made a good ' risk vs payoff ' tradeoff. Flourinated oxide reduced parasitic delays, with minimal process and manufacturing risk. Copper would have also bought an equivalent amount, but at a major manufacturing risk
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