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Technology Stocks : Intel Corporation (INTC)
INTC 35.10+2.3%3:59 PM EST
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To: Tom Warren who wrote (89749)10/8/1999 5:47:00 PM
From: Saturn V  Read Replies (1) of 186894
 
Ref-<..performance bottleneck is a L2 miss, and the L2-main memory interface.
Perhaps rambus will look a little better in this light. >

I agree .

With SSE where the pages are prefetched, the memory bandwidth (not latency!) becomes the bottleneck. Thus the Rambus becomes a performance booster if coupled with SSE Enabled Compilers. Thus I was relieved to see Tench's slide from MPF which indicated that a SSE prefetch compiler was operational.

Merced with its extensive prefetch capability will also benefit significantly from the high bandwidth of RAMBUS. The Six instruction per clock execution engine, which chew up a lot of memory bandwidth!

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