RE: <Of all the arguments you have against Rambus, this is one that really ought to be dropped. Following your line of reasoning, the CPU bus really ought to be 256 bits wide instead of 64-bit, because the L2 cache is accessed 32 bytes (256 bits) at a time. Why squeeze 256 bits onto a 64-bit bus?>
Well, there are chips with 256-bit data buses and it provides higher performance, but they're too expensive for the PC industry (but OK for servers). 486, PI, PII, PIII all have 64-bit buses. It makes sense for the memory to match it.
RE: <The point is that the CPU bus interface is independent of the memory interface. Who cares whether the CPU bus is 64-bit, or any other size for that matter, as long as the memory subsystem has enough bandwidth to feed it?>
But that bandwidth is wasted. The 64-bit bus could be fed with 4 memories in parallel at 1/4 the bandwidth per pin at no performance loss. Mux'ing down to 16 bits add no performance at all and increases latency. Unless granularity kicks in or the pin saving makes a major difference the 800 MHz is just added risk along with huge testing problems and reduced reliability -- with no benefit!
Tench, if you were architecting a memory for a PC -- not a game, not a graphics card, not anything else -- would you mux down to 16 bits? |
