Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Process Boy who wrote (75843)	10/18/1999 3:17:00 AM
From: THE WATSONYOUTH	Read Replies (4) of 1571399

Paul - <A Local Interconnect layer has nothing but thermal oxide protecting the polysilicon/CoSi gates and diffusions, and requires contacts to be etched in these features - thereby exposing the bulk silicon to contamination without phosphorus-doped dielectrics to help getter the contamination. Further, the metals used for the Interconnect layer generally have to have high meltingpoints and refractory metals are generally used - such as Tungsten - which itself is extremely difficult to process and has its own peculiar problems of adhesion, etching, etc.> PB- <Nice explanation.Intel's process is much "simpler". As you say, etching W and making W adhere consistently may be fraught with peril.> I'm not sure either of you are familiar with how AMD is practicing the local interconnect. I would guess AMD uses a doped glass dielectric (as Intel does at the contact level) with a silicon nitride etch stop and tungsten fill after appropriate liner. This is a DAMASCENE process analogous to Intel's tungsten contact hole process (the tungsten is polished - not etched) THE WATSONYOUTH

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next