Chuck,
Another DDR SDRAM forward motion - with VCM core:
Update: Nintendo console to use NEC's embedded DDR SDRAM and VCM core
ebnews.com _________________
In what reportedly is the first full-scale adoption of an embedded double-data-rate SDRAM incorporating its Virtual Channel Memory core, NEC Corp. yesterday signed a $2.7 billion deal to supply the chips for Nintendo Corp.'s new Dolphin game console.
As previously reported by EBN, NEC will build the devices on a 0.13-micron-process line the company is installing at a new fab within its Fab 8 manufacturing site in Kyushu, Japan.
Although an NEC spokesman declined to disclose specific performance or density data, sources said the embedded DDR device will be capable of a 3.2-Gbyte/s data transfer and integrates the VCM core developed by subsidiary NEC Electronics Inc. to further boost speed.
In addition to embedded DRAM, the chip will integrate a graphics accelerator core designed by ArtX Co., Palo Alto, Calif. The Dolphin game machine will be powered by the Gekko microprocessor, a 400-MHz customized PowerPC device from IBM Corp., which won out over the NEC MIPS 4300 processor used in existing Nintendo boxes.
Having already received JEDEC approval for a single-data-rate SDRAM using its VCM technology, NEC is in the process of formalizing a DDR VCM specification.
The new production line will use extended 248-nanometer krypton fluoride laser lithography and copper interconnects, the NEC spokesman said. NEC's Sagamihara development fab already is in pilot production using copper at 0.15-micron linewidths. The Kyushu line, slated to start production in 2000, will have a monthly capacity of 10,000 8-in. wafers.
The same 248-nm extended-0.13-micron design-rule lithography tools are being installed in a new NEC logic fab in Yamagata. The fab also will be the first to use the company's UX4 single system-on-a-chip production system, beginning next April.
NEC said the UX4 process solves one of the most perplexing production problems for system-on-a-chip designers: the fabrication of disparate logic and memory functions on the same die. NEC said it has redesigned the basic transistor structure of a system-on-a-chip, optimizing both the logic and memory architectures by changing the on-current and the leakage current. The changes do, however, involve additional mask steps.
The first UX4 processing at 0.13-micron design rules will begin next April at Yamagata with a capacity of 6,000 wafers a month.
ebnews.com _________________
Goutama |
