Carl,
Very technical...
By the way, I came upon a post that looked to me like it accurately described the Rambus technical problem. I posted a copy of it over on the AMD/INTC/RMBS &c., thread, but it really hasn't gathered much comment.
Basically, the claim is that there is an output current drive compliance problem. Reflections on the rambus data channel cause the "launch voltage" to differ according to previous bus activity. Some chips have trouble driving the bus due to the signals from other chips.
If this is the problem, and, if not, it seemed like the best faked technical leak I've seen in a long time, then rambus will never get 3-RIMMs to work (without reengineering the memory chips,) and will probably, in addition, have field failures in the 2-RIMM boards as well (in my opinion).
I saw your post to the other thread and I have given it a lot of thought.
First, it clearly comes from someone who understands a lot about how Rambus works, which gives it a lot of apparent credibility.
The essence of the issue is that when the controller reads from a memory chip the signal propagates towards the controller where it is reflected back down the bus. (The signal also propagates in the other direction and is absorbed by the termination resistors.) When two signals are superimposed - like the original signal and its reflection at the controller terminals which are unterminated, the voltage doubles. The reflected signal (at its original level again) goes back to the termination where it is absorbed and disappears. If it happens that a subsequent memory read requires that data is placed on the bus just as that reflection is passing by then the voltage will again double momentarily. Hence the output transistor of the memory chip will have to drive the same current as before, but at a different voltage. If it fails to do this by a large enough margin, then an error will occur - but only for chips in certain positions along the bus. There is nothing magical about having two signals passing through each other on one circuit without significantly interfering with each other - it happens all the time in the telephone system.
I do not think this is the problem, UNLESS there is a severe impedance mismatch on the offending motherboards which could give rise to multiple reflections between the controller and that mismatch. Such reflections would in places greatly increase the bus voltage and might take the driver transistor out of its linear(ish) working range.
Exact superposition of transmitted and reflected signals occurs when the round-trip time to the controller and back to the next transmitting chip equals one clock half-period of 1.25ns for 800 Mbaud DRDRAM and multiples thereof. This corresponds to a bus length of about 17.5cm, that is a distance from the controller of 8.75cm. It also occurs all the time when the bus is very short. This means that even with one RIMM there are some chips which will experience superposition and others which will not to such an extent. As this is such an intrinsic part of the Rambus design, I cannot believe that it has not been thoroughly studied and the drivers specified accordingly.
However, there is another possibility along these lines. Suppose that a chip 8.75cm from the controller sends (at least) two successive transmissions. On the second transmission there will be a superposition of the reflected and the current transmission, doubling the voltage. This doubled voltage will propagate back towards the termination. Now suppose that another device 17.5cm nearer the termination (26.25cm from the controller) starts transmitting on the next clock edge. This device will see the superposition of the first transmission reflected from the controller, the second transmission and its own transmission, bringing the level to 1.5 times the nominal Rambus signalling level. The signal is now below the lowest voltage at which the output characteristics of the drivers is specified, so while it may still work, the margins will be much lower. The same thing would also happen about 43.75cm from the controller.
The way this works is that the bus termination voltage is 1.8 +/-0.1V, corresponding to a logic 0. When a memory output pulls the bus low to signal a logic 1 the thermal calibration ensures that the bus voltage drops by about 0.4V. The receiver threshold is 1.4+/- 0.1V, so the doubling caused by the reflection at the controller is needed to bring the signal safely below the receive threshold. The signal is now nominally 1V at the controller terminals and at any device experiencing superposition of a reflected signal. This is fine, as the Rambus output transistors are specified at voltages down to 0.9V. However, if a second superposition occurs, then the voltage will need to drop to 0.6V for reliable operation. This should still work fine, but it is outside the guaranteed characteristics of the driver transistors. Therefore a compliant device might give errors, although for most devices this would not happen.
Rambus prohibit certain combinations of operations, introducing wait states and these are probably among them. However, suppose that the combination giving rise to a triple superposition at 26.25 cm was implemented correctly but that giving superposition at 43.75cm was forgotten. Then two RIMM systems would always be totally reliable, while 3 RIMM systems might not be.
The attraction of this scenario is that it is completely consistent with all the information I have seen so far, and that, if true, would give great confidence in the reliability of two RIMM systems. Furthermore, because these critical addressing sequences are likely to be rare and never occur with some motherboard layouts and still not occur most of the times when they are possible, it explains why the problem was not detected until very late.
Sorry for the length, but I hope this makes sense.
John |
