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Politics : Formerly About Advanced Micro Devices

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To: Ali Chen who wrote (76491)10/23/1999
From: THE WATSONYOUTH  Read Replies (1) of 1574997
 
Re: "If not, and if the optimal pipeline length for
x86 architecture was found to be about 10-12-15
stages, there is little reason to believe that
any other re-shuffling or partitioning of prefetch,
decode, execute, and retire functions will result in
much faster and better performing x86 CPU than
AMD Athlon or Intel CuMine."

Ali - What's your take on Moto repipelining the PowerPC design? (currently 4 stage to I believe planned 8 stage) Would you expect significant higher MHz. How much?? Any guesses? Currently, it can only achieve 500MHz in .25um vs. 600MHz for 12? stage PIII. Clock for clock, it outperforms PIII.

THE WATSONYOUTH
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