Applied demonstrates copper interconnect process on Mosel-Vitelic wafers
By Bill McIlvaine
Semiconductor Business News
(11/04/99, 01:03:24 PM EDT)
SANTA CLARA, Calif. -- Applied Materials Inc. here reported results of a collaboration with Mosel-Vitelic Inc. that allowed the Taiwanese chip maker to achieve a high yield of chips in 12 weeks using Applied Materials' equipment and copper interconnect process flow.
Applied said it is the first time an equipment manufacturer has been able to demonstrate a complete copper interconnect on a customer's device wafers. The work was performed at Applied's Equipment and Process Integration Center (EPIC) in Santa Clara.
Dennis Yost, managing director of the process sequence integration group at EPIC, said he believed the project represented the beginning of a new business model in the semiconductor industry, one in which capital equipment makers will deliver not just single tools and processes, but “equipment suppliers can now help customers bring new technologies to market faster and more cost-effectively by offering turnkey process modules.”
“The industry is going to migrate toward not just individual tools, or pieces of equipment, but process modules, that is, optimized tools and toolsets that do a particular application,” Yost said. “We think that's going to be a trend in the industry.”
In fact Yost sees the results as the proof of what EPIC was designed to do: guarantee how Applied's processes work and deliver a “process module,” not just tools, to the customer (see Online Magazine story from Nov. 15, 1998). Since it was opened in November 1998, with 200-mm tool installation completed, the facility is now ramping a new set of 300-mm systems. The company is also moving quickly to incorporate low-k dielectrics into the copper scheme for more advanced designs.
Mosel-Vitelic, a DRAM and mask ROM maker based in Hsinchu, Taiwan, delivered a cassette of SDRAM wafers to EPIC in May for demonstration of a copper interconnect structure on its device design.
“They came to us and said, 'We would like to evaluate copper interconnect, but we don't have any tools or any experience with it',” said Yost. And from that discussion in May, we delivered wafers with two levels of copper dual damascene interconnect, which we did completely here, including lithography, and they got comparable results -- parametric and yield-wise -- on their device, compared to their aluminum baseline.”
The copper integration involved a total of 49 distinct process steps, including lithography. For the demonstration, Mosel-Vitelic used a 64-megabit SDRAM design with 0.25-micron design rules. Although not typically considered one of the first devices to utilize copper, DRAMs provided a good test vehicle for monitoring interconnect defect density, Yost explained.
Mosel-Vitelic's wafers included the transistors, the capacitor word line and tungsten bit line, as well as the tungsten plugs for connection to the first metal level of copper. Applied's EPIC facility processed two levels of copper interconnects using a dual damascene, "via first" scheme that concluded with aluminum bond pad formation and final electrical testing. Applied Materials met the expected deadline for the project, Yost said, with 95% of the processing completed in just six weeks.
Applied shipped the wafers, plus all the data and information, to Mosel-Vitelic just as if it had been on the customer's development line, Yost said.
All of this was demonstrated on Mosel-Vitelic's DRAM product, which is manufactured by ProMos Technologies Inc., its joint venture with Infineon Technologies AG, the former Siemens Semiconductor of Munich.
“I don't know if they actually want to use copper interconnect for DRAM,” Yost said. “They wanted to use that for the wafer size, and they understood the device, the performance of the device, what the defect sensitivities, and it was a very good test vehicle to understand the defect characteristics of copper interconnect.”
The copper interconnects were formed using Applied Materials' copper interconnect "process module," a complete set of processing systems that has been integrated, optimized, and characterized in the EPIC facility. The module includes Applied's Producer system for silicon dioxide dielectric deposition, Centura and Super eCentura systems for "via first" dual damascene dielectric etching, the Electra barrier and seed system, the Electra electrochemical plating system for bulk copper deposition, the Mirra chemical mechanical polishing (CMP) system, the WF-736 metrology system, and the SEMVision defect review scanning electron microscope.
Additional process steps such as wet cleans, lithography, resist processing and parametric testing were also performed at the EPIC.
A single-tool process demonstration for a customer typically takes from two to four weeks, Yost said, but Applied was able to combine a 50-step process demonstration into 12 weeks, while also meeting the customers' original electrical specifications and far exceeding the projected yield, he added.
“Some masks you have to make, and there was a process setup for their specific device, setting up our stepper and matching that to their stepper--a series of activities we had to do ahead of time to make sure the wafers flow their flow through out EPIC facility in a smooth fashion,” Yost explained.
The results: two levels of interconnect, with yields comparable to Mosel-Vitelic's chips with aluminum-based wiring.
“We call it the first complete copper interconnect demonstration by an equipment supplier on a customer's device wafers,” Yost said. “We've actually run a number of customer wafers here at Applied, but this is the first time we've had a customer come in, give us their wafers, we ran one lot and when it came out we got comparable yields.”
Because working with copper as an interconnect metal is complex and still moving up the learning curve, only a few large chip makers such as IBM and Motorola can go it alone. Mosel-Vitelic needed to find a low-risk, cost-effective way to speed the development of its next-generation copper design, said Yost.
“We think the industry is going to move in this direction as far as equipment suppliers supporting their customers,” he said. “It makes our equipment significantly better because it's going to match the real customer requirements as we utilize a baseline inside Applied. And it's going to improve our customers' time to market. It is going to enable any customer to get a more mature piece of equipment, closer to production-worthiness so they an introduce new technologies more effectively, and we are going to support customers who choose to get a baseline module from us, then they can modify it themselves.”
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