Just got this from BUSINESSWIRE.
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11:31 IDT announces new category of SRAM; industry's first synchronous
Dual-Port SRAM family
SANTA CLARA, Calif.--(BUSINESS WIRE)--April 14, 1997--Integrated Device
Technology, Inc. (NASDAQ:IDTI) today announced the industry's first
synchronous Dual-Port SRAM family (see table).
The new devices will be used in a wide variety of applications including
networking (e.g., hubs, routers, switches), telecommunications (e.g., PBXs,
cellular base stations), voice recognition, multimedia and graphics.
The new synchronous devices from Integrated Device Technology (IDT) are
important because they allow pipelined operations which can achieve greater
performance when transferring bursts of data, and they reduce design time by
attaching easily to synchronous DSPs, ASICs, microprocessors and controllers.
The new devices are also available in flow-through versions which are ideal
for fast random access to individual memory locations and quick transitions
from write to read operations.
"Our new family of devices was created in response to a growing trend in the
use of synchronous interfaces on DSPs and microprocessors," said Carl May,
IDT's specialty memory products marketing manager. "As processors push the
envelope for greater speed, the synchronous interface is emerging as a simple
and fast way to move data in and out of their attached memories."
IDT's new family of synchronous Dual-Port SRAMs is a highly integrated
solution that will reduce manufacturing costs, reduce design time and
eliminate the frustration for designers who have had to implement synchronous
functionality using asynchronous devices. Such modifications require a
significant increase in design time and up to a dozen extra chips including
registers, timing circuits and clock generators.
Easy Design
The synchronous interface between IDT's new dual-port memories has been
optimized for easy design and limited intervention from the processor.
For example, during a synchronous write operation, the processor needs only
to apply the address and data to the chip for a few nanoseconds (5ns), then it
is free to move on to other operations. On the other hand, conventional memory
interfaces require a processor's attention until the memory has finished
storing data (up to 35ns) in asynchronous devices of similar density.
Reading from a synchronous memory is also simple. For instance, in the case
of a burst read, the processor doesn't have to repeatedly apply an address.
incremented on each clock edge as data moves through the output registers.
Family Specifications
The new family consists of four 512Kbit devices and two 256Kbit devices,
available in x16 and x8 configurations. Both the 512Kbit and 256Kbit devices
can output data as fast as 12ns (max), which is known as the clock to data
access time. These-high speed accesses can take place simultaneously on both
ports of the device.
All devices operate from a single 5V power supply and consume 190mA
(typical) of current in an active state, and 1mA (typical) of current in
standby. Versions of the devices that operate at 3.3V are scheduled for
release in late Q2 1997.
Synchronous Advantages
The synchronous functionality of IDT's new dual-port devices is important
because it relieves attached processors from having to hold control signals
for extended periods and maximizes performance for the target application.
Simultaneously clocked input and output registers enable new data to be moved
through input registers at the same instant that data retrieved in the
previous cycle moves through the chip's output registers (diagram 1).
high performance by eliminating the need to generate new addresses for each
clock cycle. The starting address is initially loaded, then an internal
counter is automatically incremented on each rising clock edge at the same
time that data requested in the previous cycle is output. A similar sequence
is also followed for burst write operations, except that data is input (i.e.,
written) into memory.
Dual-Port Advantages
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