Rambus (RMBS) - Eagle or Penguin Message Board

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Technology Stocks : Rambus (RMBS) - Eagle or Penguin

RMBS 96.40

+5.4%

Dec 19 9:30 AM EST

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To: John Walliker who wrote (34247)	11/12/1999 1:29:00 PM
From: wily	Read Replies (1) of 93625

. Reply from Paul DeMone (emailed to me): ---------------------------------------------------------------------- First of all, let me make this perfectly clear. I am not privy to any Rambus technical material under NDA, only what is in the public domain. Secondly, for a PWB microstrip trace with characteristic impedance of 28 Ohms, the specific capacitance is around 5 pF per inch. Thus complete compensation for 2.0 to 2.4 pF of device input capacitance from the trace being "narrowed in the vicinity of memory chip connections" is hard to believe. If my critic is willing to back up this claim with a digitized hardcopy from a time domain reflectometry tests of a bare and a populated RIMM I will be happy to examine it. This approach also risks introducing non-uniformities in the channel impedance and causing signal degradation and reflections. Perhaps this might be contributing to the well publicized problems with Camino motherboards. The question of 50 Ohms vs 28 Ohms Z0 affects the specific capacitance of signal traces, and therefore the degree to which device loading will slow down the signal wavefront propagation velocity. But the basic underlying maximum speed is set by the PWB dielectric constant, not the characteristic impedance and calling time-of-flight delays "non-existent" is utter nonsense. Regardless of the degree of waveform velocity degradation from device loading the physical aspect of DRDRAM with up to 28 inches or more of difference in round trip path length between the chipset and a near device and far device causes significant addition to the read latency seen by the chipset. This is openly demonstrated by the capability of increasing tCAS in near devices by 2.5, 5.0, 7.5 and 10.0 ns under firmware/chipset control. Don't take my word for it, here's a quote from the description of the TCDLY0 and TCDLY1 control register fields from page 43 of the NEC datasheet for the uPD488448: "This adds a programmable delay to Q(read data) packets, permitting round trip read delay to all devices to be equalized" I don't know about rambus guys, but I never have the design time or silicon area to waste adding control registers and their associated functional logic to my chips to address "non-existent" system effects.

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