Ali,
The correct reason
RAMBUS is doing this is to reduce signal reflections
that would occur at trace impedance mismatches.
I never suggested otherwise.
let me suggest
at least one area that has escaped their attention.
In their RIMM design, half of the traces are external
microstrips, the other half are internal striplines.
The propagation delay along the microstrip has
lower effective electric permittivity because
about half of it is in surrounding air. Now watch:
the total RIMM propagation delay supposed to be
1.5ns, or 1500ps. On the top, all signal delays
must be matched up to 5ps, which is 0.3%. Now
what if there is misfortune of wet weather, with
100% humidity? The dielectric constant of water steam
is 1.2% higher than for the dry air, so it could
reduce the propagtion delay of external traces
by up to 0.6%, which will violate the RAMBUS
specifications! So, do not use your computer
in rainy weather, it may hang and corrupt your
data :)
If you look at RIMMDsgnGuide.pdf you will see the following statement
"Direct Rambus RIMM Module Design Guide 0.7.1 o From device to device: The RSL signals need to be routed on the inner layers (layer 3
and layer 6). The trace dimension is showed in Figure 4-9. As mentioned above there
is also a modulated trace section to increase the device-to-device spacing. The dimen-sion
of the modulated trace is shown in Figure 4-10. Note that the crosstalk noise can
be further reduced, if the signal-to-signal in the modulated section can be shielded by
a ground or a Vdd trace with the same cross-section as in the unloaded trace section
shown in Figure 4-8. The general view of the routing of this section is shown below."
So while your assertion that there could be a humidity dependent differential delay if RSL signals were split between inner and outer layer is true it is completely irrelevant.
(I would actually expect a larger effect from water vapour absorbed into the epoxy than from nearly saturated air.)
You might also like to look at page 20 fig 3-1 showing the recommended board stackup. This clearly shows signals being routed in internal layers with power, reference voltages and low speed CMOS signals in the surface layers.
Other sections of this document describe how the signals are to be brought from the surface to the internal layers at the connectors and devices.
<Perhaps you should read it yourself.>
Already done :)
Look again.
John |
