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Electronic Engineering Times, Nov 8, 1999 p1
Fuller, Brian; Wade, Will
SAN FRANCISCO - The profound impact of the communications revolution will be felt at the 33rd International Solid-State Circuits Conference here next February, as researchers edge previously lab-bound technologies into the commercial world of videophones, whizzy networks and single-chip radios.
Synopses of some 200 international papers on processes, devices and subsystems were released last week, by IEEE tradition, to preview the event. In the mix, faster SDRAMs, high-end I/O subsystems and gigahertz-class microprocessors also steal their share of the spotlight. And the rise of consumer electronics has prompted researchers to attack the problems of integrated, low-cost systems for both cell and videophones.
Nowhere are the advances more evident than in the often-ignored transistor, which is beginning to penetrate the upper-microwave frequencies-good news for data communications systems. "Only time will tell how much further these already moving boundaries can be pushed with the advent and maturation of heterojunction bipolar transistor technologies, like silicon germanium," said Kenneth Smith, a professor at the University of Toronto who serves on the ISSCC committee.
Indeed, straight silicon itself seems to be capable of 6-GHz operation, while the more exotic heterojunction bipolar transistors (HBTs), such as those made from aluminum or gallium arsenide, are pushing toward 80 GHz.
One of the more aggressive technologies emerges in a paper from Hitachi Labs (Tokyo), which describes 104-GHz SiGe HBTs used in several circuits designed for integration into full-blown systems capable of data throughput rates of 40 Gbits/second. The Hitachi research goes a good way toward the communication industry's goal of an integrated OC-768 chip set. Targeted at optical receivers, it is equipped with a preamplifier with a 45-GHz bandwidth and a 32-dB gain-limiting amp.
Heterogeneous chip making is also at the heart of an ISSCC paper jointly prepared by Bell Laboratories (Murray Hill, N.J.) and Lucent Technologies (Nuremburg, Germany). The two describe a 40-Gbyte/s demultiplexer for fiber optics built in aluminum indium arsenide/indium gallium arsenide technology.
A fully integrated SiGe OC-192 Sonet receiver for 10-Gbit/s applications will emerge from Nortel Networks (Ottawa). Engineers there envision future applications in new, higher-speed Internet services.
Cell-phone nirvana
Moving from chips to systems, the rise of consumer electronics is rearing its head in the ISSCC program. Addressing the tricky challenge of handling streaming video over a wireless network, researchers from Toshiba Microelectronics Corp. (Kawasaki, Japan) have developed what they claim is the world's first commercial single-chip programmable MPEG-4 videophone that handles both MPEG-4 and G.729/G.723.1 speech codecs.
The device, implemented in a relatively mainstream quarter-micron, four-layer-metal CMOS process, integrates 16 Mbits of embedded DRAM with three 16-bit RISC processors and consumes 240 mW at 60 MHz. The researchers claim the memory integration cuts power dissipation by 78 percent.
One of the three processors on board the Toshiba device handles video encoding (hardware acceleration for motion estimation is provided). The second executes the speech-codec function, and the third multiplexes the audio and video streams.
Attacking a mainstream consumer design issue, engineers at Broadcom Corp. (Irvine, Calif.) teamed with researchers at the University of California, Berkeley, to develop a 1-volt heterogeneous reconfigurable processor IC to cut power consumption in cell phones. The chip allows flexible implementation of baseband wireless functions between 50 and 100 Mips/mW, or eight times lower than traditional digital signal processors, the presenters claim. A prototype design, measuring 5.2 x 6.7 mm2, is implemented in 0.25-micron, six-layer-metal CMOS and consumes 1.8 mW at 40 MHz. It combines an embedded MPU with an array of computational units connected by a hierarchical configurable interconnect network.
The technology enables data rates of up to 384 kbits/s, and the low-power processors will enable 300 to 400 Mips in third-generation (3G) phones, the researchers said.
The hunt for the holy grail-a one-chip radio-continues at this conference with a what its developers call the world's first DECT "phone-on-a-chip" from researchers at Alcatel Microelectronics (Zaventum, Belgium). The 2.7-V, 0.35-micron BiCMOS IC combines digital processing with an RF front end at 1.9 GHz, using integrated A/D and D/A converters, a voltage-controlled oscillator, a low-noise amplifier and mixers. The zero-IF topology-an old-line technique-helps to minimize noise.
As the reach of wireless technologies expands, so do efforts into increasing throughput. Researchers at IMEC (Leuven, Belgium) will present a paper describing a digital 80-Mbit/s orthogonal frequency-division multiplexing (OFDM) transceiver IC for a wireless LAN in the 5-GHz band-at least eight times the data rate of current wireless LAN systems and comparable in speed to wired LANs. The transceiver, designed in a C++ flow, is implemented in 0.35-micron, 3.3-V CMOS.
It uses distributed control and clock gating to reduce power consumption.
At the network level, researchers have also tackled thorny bandwidth issues up and down the line. Eyeing the bandwidth-to-the-home problem, researchers from UC Davis, Level One Communications (Sacramento, Calif.) and Aanetcom (Allentown, Pa.) reveal the industry's first single-chip CMOS HDSL2 analog front end, which supports full T1 transmission rates (1.544 Mbits/s) over a single copper pair. Implemented in trailing-edge half-micron CMOS, the device adapts the data rate from 63 kbits/s to 2.32 Mbits/s, depending on line quality, and has a noise-free reach of more than 14,000 feet.
Speed also gets the nod from engineers looking to boost I/O for overall system improvements. Scientists at Philips Research Labs (Eindhoven, Netherlands) describe an embedded low-cost 1.2-Gbit/s inter-IC serial data link, implemented in 0.35-micron CMOS, while Stanford scholars describe a serial link that runs at 4 Gbits/s over 10 meters of 24-AWG cables, consuming 90 mW.
A paper from researchers at NEC Corp. (Sagamihara, Japan) unveils a 20-Gbit/s interface chip set to support 3,200 x 2,400-pixel resolution on a flat-panel display.
Adding to overall system performance down the road will be the next generation of GHz microprocessors. Many of the devices have already been announced, but ISSCC is providing a venue for additional details.
One of the industry's eternal speed demons-yet also perpetually underused-a 1-GHz air-cooled Alpha chip will be described. The device, dissipating 65 W, is implemented in 0.18-micron CMOS using seven aluminum interconnect layers. The design combines two different types of transistors on the same chip: a high-threshold device that offers slower speeds with high reliability, and a low-threshold device that brings greater speed but must be managed more carefully. That combination allows designers to add speed where it is needed but to keep control over the rest of the product with more-reliable components.
As designers attempt to wring every ounce of performance out of their processors, they are focusing more attention on the interconnect. This is evident in two other 1-GHz designs, from Intel Corp. and IBM. Intel will use its 0.18-micron process technology on an IA-32 architecture product, using aluminum interconnect and low-k dielectric material to crack the gigahertz barrier, with most of the tweaking applied to the wiring rather than at the transistor level. IBM is using its copper interconnect capabilities on six-layer-metal and 0.22-micron design rules in a 64-bit PowerPC chip to reach the same speed range.
In memories, designers are boosting speed with double-data-rate designs, and ISSCC papers will show this technology applied to both SDRAM and SRAM devices. The SDRAM version, from Mitsubishi, offers bandwidth of 400 Mbits per pin and uses a delay-locked-loop circuit to permit high frequency. The 200-MHz product comes in a competitive 256-Mbit density.
NEC will also discuss its success in creating a new type of SRAM cell, which uses four transistors but does not require any resistors. That will allow designers to create much denser SRAM products by decreasing the size of the memory cells, the company says. Fewer processing steps also mean less-expensive manufacturing.
Matsushita Electronics will disclose details of an ultrafast embedded DRAM that it says could boost the performance of graphics chips that often depend on embedded memory. The company says its design features access times of 8 nanoseconds, the fastest ever reported for an embedded DRAM product. A dual-port cell allows interleaved access to the memory array, which again delivers significant performance boosts over commodity DRAM designs in a cell only 1.5 to 1.8 times larger than standard DRAM cells.
Toshiba has developed a 32-Mbit flash memory chip, with access times of 90 ns, that runs on just 1.8 V. The high density is achieved with a new channel-erase scheme that keeps the memory cell size down to 0.49 square microns. High-density, low-power flash designs are strongly desired in the consumer electronics market, for battery-powered products. Toshiba is using a new bit-line-sensing scheme to limit power consumption.
The un-disk
Some of the more esoteric technology advances on tap at ISSCC target data storage and should help Moore's Law make its way deep into the 21st century. For one, scientists from IBM Zurich will describe Millipede, a technique designed to pass what are expected to be the fundamental limits of conventional magnetic-storage approaches, which are projected to peak in 2004.
In Millipede, a scanning probe that's configured as a parallel array reads 40-nm bit indentations in 50-nm-thick poly-methylmethacrylate organic films. Early results suggest that densities of 60 to 100 Gbits/inch2 can be achieved, at least 10 times denser than conventional hard-disk drives. Early results also show read data rates of 2 Gbits/s.
More information on the Feb. 6-10 conference can be found at www.sscs.org/isscc.
Copyright [copyright] 1999 CMP Media Inc. |
