Bilow, Thank you for pointing me to Fig.59. Actually the whole Samsung spec is a copy of Rambus reference specs, letter-by-letter.
As expected, there is no mystery - counters do break
when clock slides across some boundary. But now I got
the idea how they solve the domain crossing problem:
they have two modes, A (white data) and A' (grey data),
so if the domain crossing point is close to wrap,
they just choose another edge for Tcac delay counter,
and again have plus-minus 1ns of reliable
syncronization. The only thing I did not get as where
is that bit to control this switch, and how they
identify the chips that need this adjustment when
there is no means to measure the actual delay.
I guess they must assume that specifications are
maintained rigorously. So, back to the 3-rd slot
problem, the farthest chips in slot3 have the
round-trip delay of 10ns, therefore 10% variation
of propagation time may break the functionality.
Of course, the 10% is hard to break by temperature
only, but we know that there are some more stuff
that narrows that window significantly. For example,
looking at their typical signal quality, thie window
is at least half of those 10%.
<I don't think that the clock domain transfer issues are what brought Rambus down. Instead, I think the problem is with the very tight timing and margins required on all those parts.>
I am not so convinced. The time domain issues are
tightly paired with the use of common bus wires to
transfer data back-to-back from different sources
(chips). There must be all sorts of data collisions
and resulting data distortions that does not improve
setup and hold requirements. And the junction between
"unloaded" 28-ohm lines and "loaded" 56-ohm portions
is still a compromise to match unmatchable impedances,
no matter how high some people get excited about
"modulated width transmission lines".
Regards,
- Ali
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