>> The transceiver, designed in a C++ flow
I believe this means that the transceiver was designed in an emulation environment at least partially based on C++ class definitions for objects and processes in the transceiver universe.
This is becoming the default engineering scenario for complex hardware ... design by software emulation. A common scenario is that a core vendor will partner with a CAD tools vendor to offer a development environment which includes class definitions for the hardware core's features and operation. The developer implements using the core by refining the class definitions toward his upper functional edge. The class onjects typically include the hardware core functions, firmware, soft logic ... and classes for the input envelope ... the test vectors. These system provide the concept of verification, emulation, debugging, etc, etc ... all in terms of a software model more or less directly compilable to a shipping product.
The class structure of C++ makes it cool for this.
This technique is widely used in many areas: LAN emulation, software emulation, hardware emulation, etc, etc. Usage in the area of DSPs and complex silicon is especially intense.
E.G., www.cadence.com sells such an environment for a Fujitsu processor core for $625,000.
See also:
A bit of a survey...
eet.com
M0e generally...
eet.com
A specific system, (an elcheapo one, C direct to Verilog)
eet.com
The Cadence Filix project ...
eet.com
system-level design tools that Cadence Design Systems Inc. (San Jose, Calif.) is developing as part of a collaborative project called Felix are set for a public launch is January 2000, having gone through two iterations with early adopters. A paper on Virtual Component Codesign (VCC), the name given to the Felix tool suite, was presented by Frank Schirrmeister, senior technology marketing manager for codesign technology at Cadence, at IP99 Europe earlier this month. Stan Krolikoski, senior architect for codesign technology at Cadence, co-authored the paper.
Schirrmeister said version 1.0 of the VCC tools had been released to the Felix project partners and early adopters in the fourth quarter of 1998. Version 1.1, which was improved based on feedback from the partners, has been available since June of this year.
The Felix project has a strong European focus. The partners and early adopters include ARM Ltd., BMW, Debis Systemhaus, LM Ericsson, Magneti Marelli, Motorola, National Semiconductor and STMicroelectronics. Philips Semiconductors and Infineon Technologies have also been involved in Cadence's system-level efforts through a related European Union-funded project called Cosy. Hitachi is also part of the group, Schirrmeister said.
Platform-based design
Schirrmeister's paper outlined a methodology that begins well before system partitioning into hardware and software and indicates that VCC will support platform-based design. Philips Semiconductors and other companies are adopting this approach, and Cadence staffers have even authored a book on the subject, Surviving the SoC Revolution: A Guide to Platform-Based Design. The described flow also supports multiple languages representing different system views, including SDL and C/C++.
Companies cooperate on C/C++ services
eet.com
Both companies have tools that operate from C/C++ language system-level description. Easics, a spin-off from the Interuniversities Microelectronics Center in Leuven, is introducing a C/C++ system-level modeling design flow while C Level Design has tools that automatically generate VHDL and Verilog code from ANSI C descriptions. The products support the entire ANSI C language and do not require the use of class libraries, though they do require the use of style guidelines |
