SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Paul Engel who wrote (79899)11/15/1999 3:25:00 AM
From: Zoran  Read Replies (2) of 1579364
 
Paul,

The lack of metrology tools make it very difficult to measure the actual gate CD. What can be measured is the top width, which is a process control nightmare by itself at these gate lengths. The notched gate width brings additional process control factors, like the morphology of polysilicon or in situ doping if amorphous silicon is used,and etch proximity effects. From the device point of view the overlap capacitance is going to be all over the place if the notched distance is not uniform or if it differs on one side of the gate from the other. This confounds the spacer width control with another variable that can be as large as 30%. I don't expect drive current to be affected much because channel is well controlled by the halo implants. But the overlap capacitance is the factor that will determine the winner of this horse race.

Zoran
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext