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Politics : Formerly About Advanced Micro Devices
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To: Goutam who wrote (80339)11/17/1999 8:42:00 PM
From: Zoran  Read Replies (1) of 1579804
 
Goutama,

You'll have to ask Intel people about the gory details. I can only describe a generic type of a notched gate. Imagine that you deposit your gate material in two steps. The first layer is doped (to improve poly deplition in n-channel devices and to enable very shallow extensions later on), the second one is undoped polysilicon. The ratio of both thicknesses has to be determined during process optimization. Next, the gate is patterned and etched. Doped gate material etches faster therefore creating a gate in a shape of a fat T. The notched part is thinner and defines the channel length.

The advantages of this approach might be:
- to print smaller n-channel transistors than conventional gates. (One can also predope p-channel transistors but the notch will be smaller since p-type poly/amorphous silicon etches slower than n-type doped, although still faster than undoped one)
- to reduce gate resistance
- to enable larger area to put gate contact on
- to have a knob to play with gate to source and gate to drain capacitances

The disadvantages might be (a part from my theoretical results that show that control of some crucial device/circuit parameters is worse):
- no available metrology that can measure the final gate CD of notched gate without being destructive
- automated process control (which is basically compensating gate CD variations with subsequent processing steps) is not possible.

Again, I want to emphasize that I don't claim that Intel cannot control that notched gates. My results are theoretical and a job of an engineer is to achieve what is theoretically impossible, in this case obtaining better manufacturability of notched gates.

Zoran
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