Tenchusatsu,
<Hah hah. It's nice to see that you are adding patronizing remarks to all of your so-called inside information regarding Intel's confidential projects, roadmaps, and schedules.>
Actually that was not patronizing at all! It was plain cheapshot. Sorry.
<Thankfully, most of your "inside info" is off-the-mark, ...>
Some of the things that I wrote on this thread before the information became public include Wilamette architectural tidbits, last Wilamette slip, Amador info/status (first ever public mention of Amador as far as I can tell), Pinecrest info/status (first ever public mention of PineCrest as far as I can tell), RDRAM potential customer problems before Sep release, etc. And in some of these cases it was very clear to me that even most Intel insiders (you included) know what was going on. So, may be you might want to provide some examples where my info was wrong. If you say I am off the mark on most of the stuff without substantiation that does not exactly stick. (actually my Intel sources are very reliable - far more reliable than AMD sources - so much so that sometimes I ask them for AMD info)
<Coppermine seems to be competing very well for the time being, ....>
I continued to be amazed that people find a 0.18u 733MHz chip using an expensive non-shipping platform being roughly even with a 0.25u 700MHz chip from competitor and see that as "competing very well". To quote an IBM Product Manager from CNET - ""They're going to make Intel squirm," he said of upcoming AMD chips. "
<And in the end, all this chest-thumping about schedules isn't going to mean squat, as long as the product meets or exceeds the markets expectations at the time of its release. Think Willamette won't?>
I am sorry but you were the one thumping your chest by saying how wrong I was about my simple take on Wilamette schedule. First let'em tape it out. We have at least an year to figure that out if meets or exceeds the market's expectation. Don't we?
Chuck |
