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To: Frank A. Coluccio who wrote (42)	12/4/1999 4:10:00 PM
From: Jay Lowe	Read Replies (1) of 68

Yow ... more massive inter-thread parallelism ... so here we see a design concept whereby the intelligent caching is instanced as "URL switching". Reference discussion on FCTF starting around Message 12187768 I don't get the bit about the ASIC ... is an ASIC really required to process the dependency tree ... That seems like overkill ... what's wrong with any ole fast micro, or several? Ah, well, sorting through 37,000 pages/sec might be outside the range of generalized processors ... I ain't convinced ... but have to assume these guys know their business.

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