TSMC aims to jumpstart copper in foundry with 0.18-micron process
Semiconductor Business News
(12/06/99, 08:40:09 AM EDT)
HSINCHU, Taiwan --To convince silicon foundry customers that it's time to start using copper interconnects in new IC designs, Taiwan Semiconductor Manufacturing Co. Ltd. here today launched a 0.18-micron technology and a marketing campaign to create partnerships between TSMC and early adopters of two-layer copper metal processes.
TSMC said its new commercial copper process is ready for volume production following a year of prototype fabrication for several foundry customers. The two-layer copper process will be followed by the introduction of an all-copper layer interconnect process in the first quarter next year, said Sheldon Wu, senior director of field technical support for North America, based in San Jose.
The foundry company said customer designs are well underway for the two-layer copper process, which uses aluminum for the lower four levels of metal interconnects. High volumes of copper ICs are expected to be pouring out of TSMC fabs in the third quarter of 2000. After the all-copper 0.18-micron process is formally introduced early in 2000, TSMC plans to launch an introductory two-layer copper process with 0.15-micron design rules in the second quarter next year.
A 0.13-micron copper process is slated to be available from TSMC in the second quarter of 2001. This technology will most likely be introduced with all layers available in copper since metal lines are shrinking to the point that electromigration becomes a major reliability concern, Wu said.
With today's formal introduction of the two-layer copper 0.18-micron process, TSMC claims to be the first pure-play foundry to offer the metal as a commercial technology. Crosstown rival UMC Group has also announced copper processing capabilities over the past year, and it has also been producing engineering prototypes of ICs with two and three layers of copper interconnect for a number of customers, said Jenkon Chen, senior department manager for logic, technology and process development at UMC in Hsinchu. UMC expects the initial copper IC designs to enter volume production in the middle of 2000, according to Chen.
While the world's two largest silicon foundry companies are racing each other in near-lockstep fashion, TSMC said it now is pushing copper into the mainstream by offering incentives to customers willing to move ahead with the initial two-layer copper process. The 0.18-micron process uses fluorinated silicon glass (FSG) as a low-k dielectric insulator between metal layers to help reduce capacitance, Wu said. The same FSG dielectric material is also being used in TSMC's 0.18-micron all-aluminum process.
The two-layer copper process is being marketed as a technology for sharing "risk" between TSMC and early adopters. "We call this 'risk' production," said Wu, explaining that the concept is to take a conservative step towards copper processes at this stage in the technology.
"This means the new technology has passed the process level of qualification with a TSMC test vehicle, and we have passed some level of device type reliability/qualification," he said. "However, it requires our partner [customer] to verify the long-term reliability requirements with their own real design."
TSMC has developed its two-layer copper process to be fully compatible with design rules for all-aluminum ICs at the 0.18-micron technology node. "This allows our customers to readily switch existing designs from aluminum to copper," Wu explained.
In addition, TSMC said it offering pricing incentives to early copper users, but company officials would not discuss specific prices in the program, except to say that the foundry was not charging a high premium for the metal. In fact, an IC with six-layers of aluminum interconnect could be priced higher than the same design in the two-layer copper process, hinted one TSMC official.
TSMC has partnered with a number of fab equipment suppliers to accelerate the commercial availability of copper processes, Wu said. Applied Materials Inc. in Santa Clara, Calif., has been a chief contributor in TSMC's copper process development since the foundry company set up its R&D in July 1998. (Meanwhile, foundry rival UMC has based its copper processes on tools from Novellus Systems Inc. and its coalition of equipment suppliers, according to company managers.)
The 0.18-micron copper process will be released to production initially in TSMC's 8-inch fabs, located in the Hsinchu Science-Based Industrial Park. Full production is expected to include TSMC's Fab 6, located in Taiwan's new Tainan Science-Based Industrial Park in the southern part of the island.
By the third quarter of 2000, TSMC said it will be able to fabricate 40,000 copper layers per month. This capacity is roughly greater than 6,000 eight-inch wafers a month. In 1999, TSMC had copper-processing capacity installed for a total of about 10,000 wafers, according to Wu.
TSMC declined to discuss which applications will appear with the two-layer copper processes, except to say they will include a broad range of designs for computing, communications, and consumer products. The early adopters are expected to be in high-performance microprocessors, fast SRAMs, and powerful digital signal processors (DSPs), Wu said.
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