SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Elmer who wrote (82647)12/12/1999 12:08:00 AM
From: Petz  Read Replies (1) of 1572957
 
EP, re:<the speed of any individual die is determined at final test and has nothing to do with the wafer>

This couldn't be done with the original PIII's because the L2 cache speed (SRAM) had to be selected before final packaging. I thought perhaps that each batch or each wafer might have a target maximum speed determined by sampling, and that no die on that batch would be tested at higher than the target speed.

Doing it this way you could save some test time at the expense of underbinning some parts. If the variation in Fmax, within a wafer or between wafers in a batch, is large, then you could wind up underbinning a lot of parts, leading to overclocking stories like we've read about.

Petz
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News