Dan, <If I am mistaken, I'd be interested in hearing why.>
You are not mistaken, Dan. There is no need to
argue with that arrogant but fairly ignorant
youth. He is doing what he told to, without
any own afterthought.
I was trying on several occasion to tell him
that the pure bandwidth is not the bottleneck
in most applications. The "streaming large blocks
of data" is the dying Intel mantra to justify
their attempt for Unified Memory Architecture
with AGP as a primary "streaming device" to
pump texture maps only (that need no processing),
and with "Intel inside CPU" as a primary graphics
processor.
We all know that the demand for 3D has shifted
this paradigm from UMA to hardware accelerators
with continuously increasing LOCAL memory
(since the only local memory can provide the
necessary bandwidth for modern video processing).
The little relevance of raw bandwidth was proven
in practice during several transitions in system
memory technology, from FP to EDO, then from EDO
to SDRAM, and now we are witnessing another one
- from SDRAM to RDRAM. In all cases the raw
bandwidth was increased by no less than a factor
of two, but the resulting system performance gain
was in the range of 3-10% only.
Even more, even now a x86 CPU has no internal
means to fully utilize even the existent memory
bandwidth of regular 64-bit-wide SDRAM.
Why this is important? Because if the "streamed
data" would have no need to be processed by
a CPU, the whole server business could be
done by a simple hardware switch-multiplexor!
No need for Itanic or Athlon-Sledgehammer!
As we all know, this is not the case whatsoever,
and at least a CRC needs to be calculated and
checked on every data packet, which require
a full-blown CPU intervention, not talking
about more intelligent stuff like routing
or content processing. Maybe Intel has some
ideas how to separate raw "streaming" from
intelligent content processing using some
hardware means, but I am not sure if it
bodes well with current software layers
and tendencies.
Therefore, all his pomposity and claims
about holly chipset designability is a BS.
Regards,
- Ali |
