Startup takes new approach to
verification
By Richard Goering
EE Times
(12/15/99, 3:51 p.m. EDT)
SANTA CLARA, Calif. ? An engineer's curiosity has led to a well-funded EDA
startup that's quietly developing a new type of hardware-assisted functional
simulation system. The company, Tharas Systems Inc., plans to roll out its
Verilog acceleration environment in early 2000.
With some $7 million in investment capital, Tharas Systems is unusually
well-positioned. Investors include such EDA industry luminaries as Andy
Bechtelsheim, vice president of Cisco Systems; Rajeev Madhavan, president of
Magma Design Automation; and Prabhu Goel, founder of Verilog originator
Gateway Design Automation. Goel serves on Tharas' board of directors.
Steve Carlson, a founder of Escalade Corp., recently came on board as Tharas'
chief executive officer. But the company's real roots come from the frustrated
efforts of Subbu Ganesan ? now chief technology officer at Tharas ? to find a
suitable emulation or acceleration system when he was running a VLSI design
group at ZeitNet (since acquired by Cabletron).
"Subbu had really large simulation problems," said Carlson. "He looked at
everything available, and nothing worked for him. He concluded that interconnect
was the issue. These [emulation] boxes use a lot of parallelism to achieve a
speedup, but the interconnect between the parallel units was done in a
complicated or expensive way."
Drawing on concepts from the networking industry, Ganesan came up with a new
interconnect approach that uses ASICs rather than FPGAs in what is essentially
a memory-mapped architecture. The result will be a hardware-assisted verification
system that runs more slowly than emulators, but claims lower costs, ease of
use and direct integration with current verification tools.
Since the product will normally speed up a host Verilog simulator, it doesn't really
fit into the "emulation" category. "Acceleration has a bad connotation, but what
we're really looking at is an RTL accelerator," said Carlson. "We're making RTL
simulation faster."
"It's kind of a combination of emulation and acceleration, which is very unique,"
said Madhavan. "The designers came from a field outside EDA and solved this
problem in a way no one has solved it before."
RTL focus
Tharas isn't releasing product details yet, but Carlson said the accelerator will run
from 3,000 to 100,000 cycles/second and offer verification for "many millions" of
gates. The product will handle behavioral, RTL and gate-level Verilog but the focus
is clearly on RTL verification.
Goel said Tharas' product will fill a "huge gap in the middle" for customers who
are looking for high-performance simulation, yet don't want to pay hundreds of
thousands of dollars for a big emulation system. Further, he noted, the Tharas
product will have extremely fast compilation times, making overall turnaround
times much shorter than for large emulation systems.
"What is so interesting to me," said Goel, "is that the architecture is very
counterintuitive. It's extremely memory-intensive but with very little logic. It does
not require any reconfiguration of FPGAs. The logic of the RTL is basically
compiled into memory with very little logic operation going on."
A big selling point for the Tharas solution, said Carlson, is that designers can
continue to use all of their existing verification tools. In addition to a host Verilog
simulator such as NC-Verilog or VCS, they can use their existing third-party
debugging tools, test-bench-generation tools and C language models.
"You plug this solution into your system and simulation just happens faster.
There's no coding style or anything else you have to change to get the
acceleration benefit," said Carlson.
Simulation acceleration has been a dwindling business in recent years. But
Carlson thinks there's an opening for a next-generation approach. The original
acceleration companies, he said, never made the successful transition to RTL
design, and big jumps in workstation performance made their solutions less
attractive. But now, he said, workstations are "running out of steam" as EDA
applications stretch memory limits.
Still, jumping into the specialized hardware business is a daunting prospect for a
19-person startup. Carlson said that Tharas will outsource nearly all of its
manufacturing. He had high praise for Oki Semiconductor, Tharas' ASIC supplier.
"They were willing to engage with a small team of designers on a pretty complex
design, when most suppliers saw the business as too risky," Carlson said.
The challenge now is to set up a marketing organization, but Carlson is
optimistic. "There's a real opportunity for us to be the standard platform for
executing simulation," he said. "If we could get these bundled into workstations
that are being sold for simulation, there's a huge market potential."
The company's name comes from a Sanskrit word for "rapid progress or velocity." |
