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Politics : Formerly About Advanced Micro Devices
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To: Elmer who wrote (84980)1/4/2000 5:53:00 PM
From: kash johal  Read Replies (2) of 1572371
 
Elmer,

Re:": "Frankly the issue with the K6-3's methinks was the dumb cache design without redundancy giving poor yields. Hopefully AMD has learnt this lesson well."

I think you meant to say without enough redundancy, as was claimed in an article published a few weeks ago. If true, and I think it is, this says that AMD does have problems with large integrated caches. In fact their defect density on sram arrays was worse then their models predicted. The low speeds achieved by the K63 also says they are having problems solving what are probably noise coupling issues, imho."

I agree they disn't put enough (or perhaps any )redundancy in the cache and so it became defect density limited.

AMD has CLEARLY shown by its ability to yield ATHLON's with 180mm2 die size that they have good/reasonable yields and therefore the defect density is under control.

With adequate redundancy the yield on the cache ram should be close to 100%. And I am sure that AMDs newer chips with up to 2Mb of onchip cache will have adequate redundancy and hence good yields.

As far as the bin splits of K6-3 I doubt it was cache speed limited. I suspect for a long time in 99 AMD's 0.25 micron process was yielding in the 400-450 sweet spot. They shipped higher speed grades by by taking the top 10% on 4-5M units/qtr and could ship reasonable 450-466 speed grades.

The k6-3's only got up to a few hundred K units/qtr and a 10-15% distribution on that is not enuff to make an SKU.

The bottom line is the k6 architecture sucked for Mhz scalability unlike the K7. IMHO the k6-2+ will have the cache issues fixed but the MHZ will be less than stellar.

regards,

Kash
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