Kenith, <Why don't you tell us exactly what the speed will be?>
Because he has no clue. Technically.
What would you expect from a fab "boy" working
3-rd shift, as it hints from his own post:
Message 12714520
How much can you learn from chats in smoking room? :)
Again, if someone sees/packages lots of wafers from
production lines, it does not mean that he knows
results of bin split, right? So, get easy on him...
And you are asking him about topology of clock
domains on a processor that was attempted for
re-design probably several times since
initial introductory date, somewhere in 1997...
Maybe even the key designers don't know anymore
what their timing target is? Moving target...
On the other hand, the target timing for targeted
process may be known only for a chief architect
(and his boss). Throw in uncertainties with
chip layout, RC delays, huge (apparently) on-chip
caches, more execution units, associated buffers and
bypasses, with more and more transistor budget,
with high possibility to hit power dissipation
limits, with possible inability of current software
tools to accurately model all this transistor
/interconnect budget, etc, etc...
You now the picture... |
