Reply to another question by Alfranco.
Question 2: "If we can go down to .05 microns (current best is .18 microns I believe in production) will this mean less current consumption and more compactness in these chips? If so, isn't this an advantage for operating time for hand held devices and storage capacity and even speed of operation?"
Simple answer is Yep, on all counts.
What we are talking about here is the "process" size, which I denote below as "F" for feature size. This "F" notation was used in a good article on the difficulties involved in producing the next generation of DRAMs, the 1 Gigabit chips. The meaning of F is simply that this is the width of the narrowest conductor strips that can be formed on the chips given the resolution of the wafer fabrication techniques used.
The crucial problem for higher memory cell density for DRAMs is that the capacitive memory element is much larger than the small transistor used in conjunction with the capacitor to form a memory cell. The capacitors lose their charge carrying capacity as they are made smaller, and this is a practically impossible problem to overcome as present DRAMs are made even a little denser. For ENER's OUM, however, the memory element can be made as small in width and length as F -- i.e., much smaller than a capacitive element and about the same size as the transistor junction itself.
Since memory cells must necessarily be larger than F^2 (F squared), a nice measure of the efficiency of a memory cell design (in regard to cell density) is C, where the cell size is expressed as C*F^2. C is now about 8 for lab devices, and IBM is claiming they can achieve 6, by way of forming the transistor inside the walls of the capacitor. This is a neat, but also desperate and probably expensive, trick. But, note that if wafer processing improves to give a smaller F, the size of the needed capacitor is not reduced by this change since the necessary charge-holding (capacitance) of the capacitor is not reduced. So, C would automatically increase for IBM, i.e., their cell size would not be reduced by much. For OUM chips, on the other hand, the cell size reduces a lot for reductions in F -- roughly by F^2. This is because the transistor and the OUM resistive dot both scale as F^2. If F is reduced by 1/2, the cell density goes up by 4.
This means Giga-cell chips can likely soon be made with our OUM technology. Further, due to the multi-bit capability of each OUM cell, multi-Gbit non-volatile chips should soon be possible. Wow! Giga-BYTE chips anyone? Just a SIMM or few and you have a large-capacity "electronic disk". (ECD claims that the OUM chips can be easily stacked!) Ssslllooowww, fragile, clunky hard drives -- goodbye you foul beasties!
What is the practical limit for OUM memory cell size? From the SI Board:
>Tyler Lowery mentioned that silicone is reaching it's practical limits for size reduction. Our chips would be able to store information in a cell 100x200x500 atoms big. (Also) We will be able to merge the memory and logic together on the same chip, which can't be done with flash.<
Except for very large ones, atoms are only about two Angstrom units wide, or about 0.2 nanometers. So, in nanometers, Tyler is saying 20x40x100, or in micrometers ("microns"), 0.02x0.04x0.100 (Al, because about one-half the area would be taken up by the OUM dot, these dimensions are consistent with your "0.05" micron number). Since the thickness is likely the 0.02 micron dimension, the "in-the-limit" cell area is then 0.04 *0.1 equals 0.004 sq microns. One square centimeter has 10^8 sq microns, so a 1 cm square chip could hold about 25 Gigabits (oops, sorry, GigaBytes since an OUM cell carries multibit capability). I am genuinely impressed. |
