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Politics : Formerly About Advanced Micro Devices
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To: Dan3 who wrote (91773)2/6/2000 4:55:00 AM
From: Tenchusatsu  Read Replies (1) of 1577111
 
Dan, <now you are pointing out that the coppermine cache doesn't make much sense as a match to the PIII core that it's been attached to - are you sure that that cache wasn't taken from Willamette (or Itanium)?>

First of all, I never said that the cache doesn't make sense, nor did I say that it's not a good match for the P6 core. In fact, the opposite is true; we see how much of a performance improvement Coppermine's cache provides. What I am saying is that the cache could have provided even more bandwidth if the P6 architecture allowed for it.

Second, I doubt the cache was taken from Willamette. Two very different architectures. There will be just too many peculiarities between the Willamette cache interface and the P6 cache interface to allow for such a transfer.

And third, Itanium will start off with an off-chip cache, perhaps Intel's last processor with off-chip cache. It will be custom full-speed cache, just like the current Xeon. I don't think there are plans to add an on-die cache to Merced.

Tenchusatsu
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