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Politics : Formerly About Advanced Micro Devices
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To: kash johal who wrote (91898)2/7/2000 2:51:00 PM
From: Hans de Vries  Read Replies (1) of 1578133
 
Kash Re:"kx133 chipset"

Again it shows that PC133 with CL3 is not much better then PC100 with CL2. The access to the first data from SDRAM to chipset is both 20 ns so the first of the four 64 bit words of a cache line can never arrive earlier on the Athlon. Probably only the 3rd or 4th word will arrive sooner because there is also the issue of going from the 133 MHz SDRAM clock domain to the 100 MHz DDR (200 MHz) Front Side Bus clock domain.

So: Only KX133 combined with CAS Latency 2, SDRAM makes a real difference. Having the FSB running at 133 MHz DDR (266 MHz) would streamline communication and help a lot also.

Hans.

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