Paul, the YUK Register still can't get their facts straight, even after Intel publicly announced the details of the Itanium platform. From the YUK:
As we have reported here earlier, initial speeds of Merced will be 800MHz+, the IA-64 at its heart will be a .18 micron processor, it will have cache of four megabytes plus and a frontside bus speed of 133MHz, and the CPUs will scale between 256 and 512. It will also have three levels of cache. It will not use Rambus memory, but DDR memory instead.
There are two errors here, one minor and one blatant:
- Minor error: FSB speed of 133 MHz. They forgot to mention that it's a double-pumped bus, so in AMD-speak, it's actually a 266 MHz bus. (AMD's EV6 processor interface is 100 MHz double-pumped, but everyone just calls it 200 MHz.)
- Blatant error: Itanium will NOT be using DDR SDRAM!!! (At least not the systems using the 460GX chipset, which should be the chipset of about 90% of the Itaniums sold.) Instead, Itanium/460GX will be using regular SDRAM. Intel has already said this before, yet the YUK guys still stick to the info that they obtained from "trusted sources." (hah hah)
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