Paul and Intel investors, The 64-bit chip can process six
instructions in one clock cycle -- Intel readies 800-MHz
Itanium for a midyear unveiling
What's PIII/ Athlon, three instructions per cycle?
We've heard this one before, but it always sounds good:
With e-commerce and Internet applications growing at a rapid rate, Singer said,
the Itanium will play a critical role in developing the infrastructure to support the
information age. "We estimate that the world today has only 4 percent of the server
capacity that will be required in the next several years, so that means there is 96
percent of the market left," said Singer. "We are in the beginning of a major
revolution, and we ain't seen nothing yet."
I don't think Sun can make, I mean get made, that many chips.
Tony
ADVANCED PROCESSORS The 64-bit chip can process six
instructions in one clock cycle -- Intel readies 800-MHz
Itanium for a midyear unveiling
SATURDAY, FEBRUARY 12, 2000 2:12 AM
- CMP Media
Feb. 11, 2000 (Electronic Engineering Times - CMP via COMTEX) -- SAN
FRANCISCO - Intel Corp. plans to introduce its long-awaited 64-bit Itanium
microprocessor later this year at an initial speed grade of 800 MHz. The company
revealed numerous technical details of the device this week at the International
Solid-State Circuits Conference 2000.
"This is the most significant product introduction from Intel since the 386 chips,"
said Gadi Singer, vice president and general manager of the company's IA-64
division and a key architect on the project. Singer claimed that while Itanium will be
at 800 MHz, its ability to process six instructions in a single clock cycle will make it
a higher-performing processor than the gigahertz chips.
He said the company has delivered thousands of engineering prototypes of Itanium
to more than 30 computer OEMs, as well as to numerous other vendors in the chip
set, operating system, application software and other segments.
Code-named Merced, the device will hit the market in the middle of this year,
Singer said. The processor contains 25 million transistors and is contained within
a cartridge that packs 4 Mbytes of Level 3 cache. The Itanium features a back-side
bus that allows this cache to run at the same frequency as the processor itself. The
front-side bus delivers 266 million transfers per second, which is twice the speed
seen in the 133-MHz buses found in today's high-end IA-32 processors.
The Itanium is expected to be used in servers and workstations, and Intel will
support the processor with a chip set that allows as many as four of the chips to
work together. OEMs can then pack these units together into workhorse systems
with as many as 512 Itanium chips working collaboratively.
Singer said that the chip is designed with parallel execution in mind, and each
Itanium can process up to six instructions simultaneously. Its floating-point unit can
perform 6.4 billion operations per second.
"Our design goal was to keep the chip busy every cycle," he said. "The Itanium
delivers greater instruction-level parallelism than any contemporary processor."
With e-commerce and Internet applications growing at a rapid rate, Singer said,
the Itanium will play a critical role in developing the infrastructure to support the
information age. "We estimate that the world today has only 4 percent of the server
capacity that will be required in the next several years, so that means there is 96
percent of the market left," said Singer. "We are in the beginning of a major
revolution, and we ain't seen nothing yet."
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