Elmer,
you're almost as famous as paUL!
fastgraphics.com
steve
Elmer Phud's look upon the P6 (Pentium Pro / Pentium 2) bus:
I will attempt to explain the differences between the older x86 bus architecture and the newer P6 socket8/slot1 bus architecture, and
why I and many in the systems design field see a hugh difference in the two.
First the x86 bus. This covers all x86 compatible devices up to and including the Pentium. This bus is based on bus cycles. A
processor exerts a set of control signals indicating what type of bus cycle it intends to perform. Be it a memory read/write, IO
read/write, etc. The processor maintains control of the bus until the access is complete. If there are wait states, then the cycle is
extended for however many clocks it takes for the access to complete. In a SMP system, the other processors must wait until the first
is finished before they can attempt to start a cycle of their own. There is no overlap, each must wait their turn.
For the P6 generation, everything is different. There is no such concept as bus cycle. There are instead transactions. A processor
issues a transaction, be it a request for data stored in memory, IO, PCI etc, the same type of things an x86 processor would do, but it
does not wait for the transaction to complete!! It immediately releases the bus. In a SMP system any other processor is now free to
issue their own transactions without having to wait for the first processor's transaction to first complete! In fact there is no special
order in which transactions need complete. The concept of "out of order execution" which the P6 uses has now been extended down
into the memory/IO subsystem. Instead of the old socket7 way where each processor had to own the bus until it's bus memory
request was completed, the socket8/slot1 system can now overlay transactions and accept their completion as they actually occur,
not 1 at a time as the socket7 has to. In a 4 way SMP system, all 4 CPU's could have multiple transactions in various stages of
completion while a socket7 system may still be adding wait states for a single CPU!!
For those who have bashed Intel as only bringing out slot1 so as to screw AMD & Cyrix, I must say they are sadly mistaken. When
AGP arrives and adds a new wrinkle to the memory bandwidth problems the K6 will face, the advantages of the Intel transaction
based bus architecture will be evident to those who can keep an open mind.
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