Ten, >"With the new
scalability port we can link two or more 4-way systems," Rattner said. "This allows OEMs to build 8-, 12- or
16-way systems."
Definitely good stuff for high performance systems. Does this mean that the performance penalty multiplier up to, like 16 way, will be like that of a "pure" 16 way SMP system? Like with 8 ways, you "only" get something like 0.75X8 = 6 equivalent CPUs worth of processing power, which is still great compared with a clustering penalty. That's because of overhead.
I appreciate having Intel engineers on this thread, giving us real world info about the products where they can, within NDA limits. The AMD thread, as technical as they like to be, don't have any AMD engineers, at least that have come forward. Advantage, Intel investor.
Tony |
