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Politics : Formerly About Advanced Micro Devices
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To: Paul Engel who wrote (94644)2/22/2000 7:58:00 PM
From: Epinephrine  Read Replies (1) of 1575759
 
<but I will go back and reread it with an eye toward spotting bias.>

Paul,

I have reread Johan's article and I'm glad I did. His numbers make even more sense to me now. (ie I know where he got them) He is basing his assumption on the fact that the Athlon has a dual issue FPU (2 instructions per cycle) times the number of cycles (in this case 1.2GHz) for a theoretical max of 2.4Gigaflops whereas the Willamette will have (his assumption) a single issue FPU like the PIII (1 instruction per cycle) times the number of cycles (in this case 1.4GHz...note the Mhz advantage he gave the Willamette) for a theoretical max of 1.4Gigaflops. The SSE/3DNow estimates are similar calculations based on the number of SIMD instructions the processors can issue per clock. Admitedly he is assuming that Willamette will retain the PIII's single issue FPU. but other than that all his calculations seem solidly based in documented information and sound logic. But you had said:

<You are missing the fact that Johan (Mean stuff deleted) is completely wrong.>

Are you saying that you think Willamette will get a dual issue FPU. or do you disagree with Johan that the Willamette will only have a single SSE execution unit because I think those are the only factors that would effect these theoretical maximum architectural numbers. PLEASE let me know if you are claiming that the Willamette will get a dual issue FPU.

Thanks,

Epinephrine
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