New Patent
22-FEB-00 6,028,336 6,028,336-Triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates, and methods of manufacturing such arrays
Abstract
As part of a flash EEPROM array on a semiconductor substrate, erase gates are formed in individual trenches between rows of floating gates. The erase gate is positioned along one sidewall of the trench in a manner to be capacitively coupled with the floating gates of one of the rows adjacent the trench but spaced apart from the floating gates of the other row adjacent the trench. In this way, a separate erase gate is provided for each row of floating gates without increasing the size of the array. The erasure of each row can then be individually controlled. Two self-aligned methods of forming such an array are disclosed. One method involves forming a thick insulating layer along one sidewall of the trench and then filling a remaining space adjacent an opposite trench sidewall with polysilicon material forming an erase gate for the row of floating gates adjacent the other sidewall. A second method involves anisotropically etching a layer of polysilicon that is formed over the array in a manner to conform to the trench sidewalls, thereby separating the polysilicon layer into individual erase gates carried by the trench sidewalls.
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Inventors: Yuan; Jack H. (Cupertino, CA).
Assignee: SanDisk Corporation (Sunnyvale, CA).
Appl. No.: 908,264
Filed: Aug. 7, 1997
Related U.S. Application Data
Division of Ser No. 550,887, Oct. 31, 1995, Pat. No. 5,712,179.
Intl. Cl. : H01L 29/788
Current U.S. Cl.: 257/315; 257/319
Field of Search: 257/315, 319, 320, 321, 322 |
