Re: On-die L2 caches are quickly becoming a de facto standard anyway. All future processors, whether from Intel, AMD, Compaq/Digital, Sun, or IBM, will have on-die caches.
Coppermine's L2 was a surprising and particularly nice one, though. Low latency, wider than it needs to be (why?), and not in the roadmap.
Yes, Intel got to on-die cache first, and yes, AMD will take away that advantage with Thunderbird. But then Intel will get to 20-stage pipelines first. What will AMD have after that?
At some point, managing additional pipeline stages must add more costs than benefits. Facing the example of PIII's existing 12 stage pipeline, having seen it's advantages compared to K6's 5 stage pipeline, AMD went with a 10 stage pipeline. There are probably benefits and drawbacks to each approach.
And one other thing, are all of the logic units 20 stage? If it's only the "double pumped" ALUs, then the 20 stage pipeline completes instructions in 10 clocks and the transistors have no more switching time available than Athlon's 10 stage pipeline, but the complexity in designing a 20 stage controller remains. All the costs and none of the benefits of a longer pipeline?
As far as I can tell, as an interested layman, Willamette looks like a nice design, but not an overwhelming one. And I think that getting into copper ASAP (versus waiting till it's absolutely necessary) will be a benefit to AMD.
Dan |
