SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (96166)3/1/2000 9:54:00 PM
From: Joe NYC  Read Replies (2) of 1576835
 
With these 128 bit instruction words, that contain 3 insturctions, isn't there going to be a problem with cache misses? Suppose you have these 3 instruction, each of these instructions needs some data that is sitting somewhere in memory. The compiler does not know where. Suppose 2 of them are in L1, and the third one is not even in L2 and has to be retrieved from main memory. What's going to happen with this instruction? Isn't it going to be stalled until the data is retrieved?

I guess in IA-32 architecture, the CPU would be able to execute the first 2 instructions right away.

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext