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Politics : Formerly About Advanced Micro Devices

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To: Duncan Baird who wrote ()	3/3/2000 6:19:00 AM
From: Hans de Vries	of 1571473

Intel disclosed Willamette's features way back in 1998. They where well know to AMD even before the first tape-out of the Athlon. I'm quite sure that AMD considered them for it's new designs. A 1998 MPR article from Linley Gwennap already contains the following information: - The Willamette's core is "superpipelined" to achieve a target frequency about 40% higher as the P6 with it's 12-stage pipeline. Linney Gwennap: "This statement implies that the Willamette pipeline is long enough to carry Alaskan oil" - Foster (the Xeon version of Willamette) will have a 3.2 GHz system interface (this was recently confirmed as being 64 bit x 400 MHz) - Willamette will contain a Trace Cache to keep the pipeline flowing even in programs with many branches. Some comments to this: The Willamette 1.5 GHz frequency was to be anticipated when Intel disclosed half a year ago that new process advances would bring the P6 up to 1 GHz speeds. (Advanced program of the ISSCC 1999). Originally the P6 would stop at 750 MHz and the Willamette would be the first to break the 1 GHz barrier. The "double clocked 3 GHz ALU" could have been anticipated way back in 1998. Why? Well because the time that the ALU needs to do it's job is 1 clock cycle for the P6 (and the Athlon). In the Willamette it needs 1.5 clock cycle. Just rounding this to 2 clock cycles would slow down data dependent code to 750 MHz instead of 1.5 GHz and slower then on a 1 GHz P6!. (Data dependent code are instructions that need the result of the preceding operation). Introducing half cycles with the use of a 3 GHz clock allows the Willamette to feed back the result of an operation to the next one after 1.5 cycles. Data dependent code can thus run at 1 GHz. At the same speed as the P6 instead of slower. Process engineering advances improved the 0.18 micron process by about 40% Interesting is that an 1998 Intel article states that 2.3 nanometer is the physical limit for the transistors gate SiO2 thickness. Leakage will get to high below this barrier. Intel is now using 2.0 nanometer gate SiO2 to get the P6 up to 1 GHz. (Other materials then SIO2 will be used in the future for the gate dielectricum. Thermal processing can be used to improve SiO2 uniformity and will lower the barrier even further) semiconductor.net Hans.

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