SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (99218)3/21/2000 9:24:00 AM
From: vince doran  Read Replies (1) of 1576696
 
Scumbria, Kap, Jim: Re speed increase from full-speed L2:

There are two data points that should be remembered -
1. Katmai -> CuMine > 20% increase per clock.
2. The odd DDR full-speed cache experiment reported late dec. 99, with one benchmark, on the SuperPi calc. On that bench, standard Athlon 1100 MHz = CuMine 900 MHz, but for the DDR beast, Athlon 835 MHz = CuMine 1050 MHz. That was off-chip, with 24 cycle latency, per JC. The list of SuperPi is at
www16.big.or.jp

Cheers,
Vince

P.S. Search JCs for dec with athlon ddr cache to see his post; Ace's had more detail at the time but their archive doesn't work for me.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News