SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 88.75+1.2%9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (38766)3/23/2000 5:00:00 AM
From: Ian Anderson  Read Replies (1) of 93625
 
Another important point here is that with CuMine processors the cache line size just doubled from that of earlier processors (Dont be surprised if it doubles again for Willamette).

That means SDRAM and DDR need to do two accesses from consecutive addresses, complete with the latency of a RAS cycle to send the low part of the address for the second fetch to the memory chips.

On the other hand RDRAM doesn't need a second address, this is what it does best. It just keeps sending the data at 1.6G bits/ second from consecutive addresses until you tell it to stop :)
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext