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Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 87.70-3.8%Nov 18 3:59 PM EST
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To: Ian Anderson who wrote (38767)3/23/2000 9:42:00 AM
From: Scumbria  Read Replies (1) of 93625
 
Ian,

That means SDRAM and DDR need to do two accesses from consecutive addresses, complete with the latency of a RAS cycle to send the low part of the address for the second fetch to the memory chips. On the other hand RDRAM doesn't need a second address, this is what it does best. It just keeps sending the data at 1.6G bits/ second from consecutive addresses until you tell it to stop

Actually, SDRAM accesses to consecutive addresses do not require a second RAS cycle, and the data is pipelined seamlessly without any bubbles. The core design in DRDRAM and DDR is essentially the same, and there is no reason why data should be returned at a different rate.

Scumbria
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