1GHz Coppermine won't copulate
Posted 31/03/2000 11:35am by Mike Magee
Information available publicly on the Intel Web site has confirmed that the firm's 1GHz Coppermine microprocessor cannot be used for dual processing.
Yesterday, leaked documents we saw earlier in the week, said that Intel's Lancewood motherboard would support just about every flavour of Coppermine known to humankind, except for the 1GHz chip.
At this FTPsite, and in a table on page 18, a footnote confirms that the 1GHz microprocessor will not work in tandem with another 1GHz Intel chip.
But Intel does not explain in this publicly available document exactly why putting two 1GHz microprocessors in harness will not cut it.
According to one system integrator close to Intel's plans, the reason for this is because the 1GHz Pentium III uses a different stepping to other Coppermines. As of two weeks ago, he said, that particular stepping was not rated for dual usage.
He points out that Intel, in the PDF referred to above, indicates that after 1GHz chips start to arrive in quantity, it will no longer rate microprocessors in terms of MHz. As he says: "Doesn't an official 1.066 Genuine Intel Pentium !!! with Internet Streaming SIMD instructions just slide off the tongue."
* In other Intel news, the firm confirmed yesterday that the 533A Pentium III, using the.18æ (micron) is currently being shipped alongside existing .25æ microprocessors, which will eventually be phased out. ©
theregister.co.uk
ftp://download.intel.com/design/PentiumIII/specupdt/24445315.pdf
PENTIUM © III PROCESSOR SPECIFICATION UPDATE
3
Mixed Steppings in DP Systems
Intel Corporation fully supports mixed steppings of Pentium III processors. The following list and processor
matrix describes the requirements to support mixed steppings:
ú Mixed steppings are only supported with processors that have identical family and model number as
indicated by the CPUID instruction.
ú While Intel has done nothing to specifically prevent processors operating at differing frequencies from
functioning within a multiprocessor system, there may be uncharacterized errata that exist in such
configurations. Intel does not support such configurations. In mixed stepping systems, all processors
must operate at identical frequencies (i.e., the highest frequency rating commonly supported by all
processors).
ú While there are no known issues associated with the mixing of processors with differing cache sizes in a
dual processor system, and Intel has done nothing to specifically prevent such system configurations
from operating, Intel does not support such configurations since there may be uncharacterized errata that
exist. In dual processor systems, all processors must be of the same cache size.
ú While Intel believes that certain customers may wish to perform validation of system configurations with
mixed frequency or cache sizes, and that those efforts are an acceptable option to our customers,
customers would be fully responsible for the validation of such configurations.
ú The workarounds identified in this and following specification updates must be properly applied to each
processor in the system. Certain errata are specific to the dual processor environment and are identified
in the Mixed Stepping Processor Matrix found at the end of this section. Errata for all processor steppings
will affect system performance if not properly worked around. Also see the ?Pentium © III Processor
Identification and Package Information? table for additional details on which processors are affected by
specific errata.
ú In dual processor systems, the processor with the lowest feature-set, as determined by the CPUID
Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in feature-set, the tie should
be resolved by selecting the BSP as the processor with the lowest stepping as determined by the CPUID
instruction.
In the following processor matrix a number indicates that a known issue has been identified as listed in the
table following the matrix. A dual processor system using mixed processor steppings must assure that errata
are addressed appropriately for each processor.
few pages down
PENTIUM © III PROCESSOR SPECIFICATION UPDATE
10
Pentium© III Processor Identification and Package Information
S-Spec
Core
Steppings CPUID
Speed
(MHz)
Core/Bus 11 L2 Size
(Kbytes)
Tag RAM/
Steppings
ECC/
Non-ECC
Processor
Substrate
Revision
Package
and
Revision Notes
SL3XQ cB0 0683h 800EB/133 256 N/A ECC B SECC2 10
SL458 cB0 0683h 800EB/133 256 N/A ECC B SECC2 8, 10
SL3XR cB0 0683h 800/100 256 N/A ECC B SECC2
SL457 cB0 0683h 800/100 256 N/A ECC B SECC2 8, 10
SL43F cB0 0683h 850/100 256 N/A ECC B SECC2
SL47M cB0 0683h 850/100 256 N/A ECC B SECC2 8
SL43G cB0 0683h 866/133 256 N/A ECC B SECC2
SL47N cB0 0683h 866/133 256 N/A ECC B SECC2 8
SL48S cB0 0683h 1.0B GHz /133 256 N/A ECC B SECC2 12 10
? Unless otherwise noted, all Pentium III processors in S.E.C.C.2 package have an OLGA package core.
NOTES:
1. These parts will only operate at the specified core to bus frequency ratio at which they were manufactured and tested. It is
not necessary to configure the core frequency ratios by using the A20M#, IGNEE#, LINT[1]/NMI and LINT[0]/INTR pins
during RESET.
2. These processors will not shut down automatically upon assertion of THERMTRIP#.
3. This is a boxed processor with an attached heatsink.
4. Performance-monitoring event counters do not reflect MOVD and MOVQ stores to memory on these processors.
5. These parts will not assert THERMTRIP#, nor will they shut down in the event of an over-temperature condition (e.g. Tj =
~135C).
6. Pin AJ3 is removed from these parts.
7. This is a boxed processor with an unattached fan heatsink.
8. This is a boxed processor with an attached fan heatsink.
9. These processors have not been validated in Dual Processor (DP) applications.
10. The ?E? and ?B? designators distinguish between Pentium © III processors with the same core frequency but different
system bus frequencies and/or cache implementations.
B = 133MHz System Bus
E = Processors with ?Advanced Transfer Cache? (CPUID 068x and greater only if a frequency overlap exists)
If, for a given core frequency, Pentium III processors are only available with one system bus frequency and one cache
implementation, the above designators will not be used (e.g., not all processors with ?Advanced Transfer Cache? will have
the ?E? designation).
11. Speeds will be marked as MHz up to but not including 1.0 GHz. Speeds 1.0 GHz and above will have the GHz marking.
12. These processors cannot be used in Dual Processor (DP) applications.
LMAO!!!
Milo |
