RAMBUS IS NOW A TWO-TRICK PONY, HAS A NEW PRODUCT!
Rambus steps up evolution to communications-IC supplier
By Mark Hachman
Electronic Buyers' News
(04/05/00, 11:33:08 AM EST)
Throw out all your assumptions about Rambus Inc. -- it isn't just a DRAM designer any more.
In the wake of a plan first disclosed last December, Rambus yesterday announced a two-pronged strategy for the communications market: selling conventional Direct Rambus DRAM as the memory of choice for a new breed of network processors, and designing a new serializer/deserializer interface for line cards used in routers and switches.
While the strategy may seem a novel one for Rambus, executives noted that a 1997 prospectus describes the Mountain View, Calif., company as marketing a high-speed, chip-to-chip interface technology. ?Nowhere does that mention memory,? said Rambus president David Mooring in a press conference late Tuesday.
The strategy also offers Rambus a convenient escape route, given the lukewarm reception the company has enjoyed in the PC market to date. DRAM manufacturers have complained about high price premiums relative to the competing SDRAM and double-data-rate DRAM standards. Partner Intel Corp. has had repeated difficulties manufacturing Rambus-enabled PC core-logic chipsets, and Intel's forthcoming Timna integrated processor uses an SDRAM interface instead of the Direct RDRAM interface that was originally expected.
Still, supplies of Direct RDRAMs are increasing, and analyst Martin Reynolds of Dataquest Inc., San Jose, predicted that ?by 2001, Rambus will be pretty much required by a performance microprocessor.?
Just as NeoMagic Corp.'s embedded DRAM technology has extended beyond notebook graphics, Rambus executives view their expertise as one that transcends DRAM. ?In 1997 we debuted our chip-to-chip interface technology,? said Kevin Donnelly, vice president and general manager of the Consumer and Communications Products Division at Rambus. ?We're pleased to announce the first use of Rambus technology in a non-DRAM application.?
That use will be the Rambus-designed serializer-deserializer, essentially the interface used by the line card in a router or network switch. The line card is an add-on card typically containing a network processor, which accepts packetized data from multiple sources, figures out where to direct it, and routes it on its way via a passive backplane similar to a PC motherboard. Rambus' argument is that as networks upgrade to high-speed 10-Gbit/s optical networks like OC-192, the line card will become increasingly important to keep data moving at maximum speed.
?Switches and routers have board problems which they've attempted to solve for a number of years, and as OC-192 approaches these have become a real problem,? Donnelly said.
The serializer-deserializer, or ?SerDes,? as Donnelly termed it, will offer 12.5 Gbits/s via four differential pairs of connections, at 3.125 Gbits per pair. The SerDes is the third piece of technology Rambus is currently licensing to other chip companies and foundries, following the Rambus ASIC Cell (RAC) and the corresponding Direct Rambus DRAM interface. An eight-connection or octal SerDes cell is in development, Donnelly said, offering up to 5 Gbits/s total bandwidth. A 30-in. backplane will be permitted.
Rambus executives said they leveraged a significant amount of the signaling and design work on the RAC and Rambus DRAM interface in designing the SerDes. Still, analysts quickly pointed out that Rambus is once again breaking ground in a new market, a strategy that historically has met with some resistance.
?If I were to start with a clean slate, would I build a long-latency, serial, differential device [for the networking market]?? asked Peter Glaskowsky, analyst with MicroDesign Resources Inc., Sunnyvale, Calif. ?I'm a little dubious about that.?
No design wins have been announced for the SerDes, and network-processor industry representatives at the event chose to talk about their use of Direct Rambus DRAM as a memory interface to their devices -- the other half of Rambus' strategy. To date, network processors have typically been designed to access fast SRAM.
Four companies -- PMC-Sierra's Extreme Packet Devices group, Sitera, Switchcore, and Vitesse Semiconductor's new Orologic subsidiary -- have indicated that their network processors will connect to conventional 400-MHz Direct Rambus memory, also known as "PC800" Direct RDRAM in the PC space.
Still, the field of design wins disclosed yesterday was populated more by companies with announced products than by those actually shipping silicon. Sitera, for example, only announced and sampled its first Prism IQ2000 network processors April 2. When asked why PC partner Intel Corp. and its established IXA network-processor infrastructure were not identified as embracing Direct RDRAM, Donnelly said only that other design wins have not been announced.
Cindy Lindsay, in charge of strategic alliances at Sitera, Longmont, Colo., said that the Rambus interface will be most useful in lookup tables in a new breed of "policy engines" companies are building into network processors.
?It's a way of dynamically allocating packets in a network,? Lindsay said. ?Each packet must be compared against a whole hierarchy of [instructions]. For example, there might be no game playing on the network from 9 to 5. Or, during the two days at the end of the month, a [network administrator] might say OK, manufacturing gets 90% of the bandwidth now.?
The pin count associated with DDR SDRAM was found to be a ?huge? negative, Lindsay said, while the Rambus architecture is pin-efficient and offers high performance. While Sitera's Prism still contains an on-chip SRAM connection, she noted that SRAMs themselves remain on allocation.
Rival Orologic Inc., Morrisville, N.C., expects its own test silicon back from the fab in a couple of weeks, said Stan DiPretoro vice president of sales. ?For us, it's all about speed,? he said.
Orologic said its Rambus-enabled network-processor technology will be best implemented in so-called ?edge switches,? which operate at the edges of a WAN. |
